1. Field of the Invention
The present invention relates to a method for forming a gate oxide of a semiconductor device, and more particularly, to a method for forming a gate oxide of a semiconductor device with a triple gate oxide having multiple thicknesses.
2. Background of the Related Art
Although conventional semiconductor memory devices have used a gate oxide film having a single thickness, system IC logic products use a semiconductor device having various operating voltages by using gate oxides having multiple thicknesses.
That is, the semiconductor device employs a triple gate oxide structure which includes a thick gate oxide formed in a high voltage region, a thin gate oxide formed in a low voltage region and a gate oxide thinner than the gate oxide formed in the high voltage region, thicker than the gate oxide formed in the lower voltage region and formed in a medium voltage region to achieve appropriate insulation.
FIGS. 1a, 1b, 1c and id are cross-sectional views illustrating a conventional method for forming a gate oxide of a semiconductor device.
Referring to FIG. 1a, an isolation layer 110 and wells 120 are formed in a semiconductor substrate 100 on which a first region A where a first gate oxide having a first thickness will be formed, a second region B where a second gate oxide having a second thickness less than the first thickness will be formed and a third region C where a third gate oxide having a third thickness less than the second thickness will be formed are defined.
Referring to FIG. 1b, a first oxide film 130 is formed of TEOS (Tetra Ethyl Ortho Silicate) by a predetermined thickness on the semiconductor substrate 100. A photoresist pattern 140 that selectively exposes the second region B and the third region C is formed on the first oxide film 130 and photolithography is performed using the photoresist pattern 140 as a mask to selectively remove a portion of the first oxide film 130, which is formed on the second region B and the third region C.
Referring to FIG. 1c, the photoresist pattern 140 is removed and a second oxide film 150 is formed by a predetermined thickness on the overall surface of the semiconductor substrate 100. Then, a photoresist pattern 160 that selectively exposes the third region C is formed on the second oxide film 150 and photolithography is performed using the photoresist pattern 160 as a mask to selectively remove a portion of the second oxide film 150, which is formed on the third region C, as illustrated in FIG. 1d. 
Subsequently, a third oxide film 170 is formed by a predetermined thickness on the overall surface of the semiconductor substrate 100.
Accordingly, a first gate oxide 180 including the sequentially laminated first, second and third oxide films 130, 150 and 170 is formed in the first region A, a second gate oxide 190 including the sequentially laminated second and third oxide films 150 and 170 is formed in the second region B and a third gate oxide composed of the second oxide film 170 is formed in the third region C.
To form this triple gate oxide having multiple thicknesses, three masking processes and three deposition/etch processes are required, as described above. This increases the manufacturing cost and time and decreases production yield. Furthermore, it is difficult to secure a margin for a patterning process using photoresist as the integration of the semiconductor device increases.
Moreover, a cleaning process is required to selectively remove the oxide films to cause generation of a large number of particles on the surface of the semiconductor substrate.
Furthermore, in the case of the TEOS oxide film formed in the high voltage region A, dangling bonds or other point defects at the TEOS interface are not cured even though thermal budget is applied thereto, and thus a gate leakage current increases. In addition, deteriorated interface characteristic increases interface trap charge (Dit) density to decrease NBTI characteristic.
Moreover, when only the TEOS oxide film is formed thick, uniformity of the TEOS oxide film is decreased to degrade threshold voltage characteristic of a high voltage element formed in the high voltage region A so as to decrease electrical characteristic of the high voltage element.